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/*
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* This programmer uses AT91' GPIO lines
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*
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* 2006 by Carlos Camargo
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* 2007.May.10 Andres Calderon
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* 2009.Aug.26 Jose Francisco Quenta
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*/
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#ifndef ECB_AT91_H
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#define ECB_AT91_H
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#define MAP_SIZE 4096Ul
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#define MAP_MASK (MAP_SIZE - 1)
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#define PIOA_BASE 0xFFFFF400
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#define PIOB_BASE 0xFFFFF600
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#define PIOC_BASE 0xFFFFF800
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#define PIOD_BASE 0xFFFFFA00
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#define PB0 (1 << 0)
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#define PB1 (1 << 1)
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#define PB2 (1 << 2)
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#define PB3 (1 << 3)
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#define PB8 (1 << 8)
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#define PB9 (1 << 9)
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#define PB10 (1 << 10)
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#define PB11 (1 << 11)
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#define PB16 (1 << 16)
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#define PB17 (1 << 17)
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#define PB18 (1 << 18)
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#define PB19 (1 << 19)
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#define PB20 (1 << 20)
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#define PB21 (1 << 21)
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#define PB22 (1 << 22)
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#define PB23 (1 << 23)
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#define PB24 (1 << 24)
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#define PB25 (1 << 25)
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#define PB30 (1 << 30)
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#define PB31 (1 << 31)
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#define PC0 (1 << 0)
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#define PC1 (1 << 1)
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#define PC4 (1 << 4)
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#define PC5 (1 << 5)
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#define PC6 (1 << 6)
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#define PC7 (1 << 7)
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#define PC8 (1 << 8)
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#define PC9 (1 << 9)
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#define PC10 (1 << 10)
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#define PC11 (1 << 11)
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#define PC16 (1 << 16)
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#define PC17 (1 << 17)
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#define PC18 (1 << 18)
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#define PC19 (1 << 19)
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#define PC20 (1 << 20)
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#define PC21 (1 << 21)
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#define PC22 (1 << 22)
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#define PC23 (1 << 23)
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#define PC24 (1 << 24)
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#define PC25 (1 << 25)
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#define PC26 (1 << 26)
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#define PC27 (1 << 27)
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#define PC28 (1 << 28)
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#define PC29 (1 << 29)
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#define PC30 (1 << 30)
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#define PC31 (1 << 31)
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typedef volatile unsigned int AT91_REG;
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/* Hardware register definition */
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typedef struct _AT91S_PIO {
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AT91_REG PIO_PER; /* PIO Enable Register */
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AT91_REG PIO_PDR; /* PIO Disable Register */
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AT91_REG PIO_PSR; /* PIO Status Register */
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AT91_REG Reserved0[1];
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AT91_REG PIO_OER; /* Output Enable Register */
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AT91_REG PIO_ODR; /* Output Disable Registerr */
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AT91_REG PIO_OSR; /* Output Status Register */
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AT91_REG Reserved1[1];
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AT91_REG PIO_IFER; /* Input Filter Enable Register */
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AT91_REG PIO_IFDR; /* Input Filter Disable Register */
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AT91_REG PIO_IFSR; /* Input Filter Status Register */
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AT91_REG Reserved2[1];
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AT91_REG PIO_SODR; /* Set Output Data Register */
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AT91_REG PIO_CODR; /* Clear Output Data Register */
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AT91_REG PIO_ODSR; /* Output Data Status Register */
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AT91_REG PIO_PDSR; /* Pin Data Status Register */
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AT91_REG PIO_IER; /* Interrupt Enable Register */
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AT91_REG PIO_IDR; /* Interrupt Disable Register */
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AT91_REG PIO_IMR; /* Interrupt Mask Register */
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AT91_REG PIO_ISR; /* Interrupt Status Register */
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AT91_REG PIO_MDER; /* Multi-driver Enable Register */
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AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
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AT91_REG PIO_MDSR; /* Multi-driver Status Register */
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AT91_REG Reserved3[1];
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AT91_REG PIO_PUDR; /* Pull-up Disable Register */
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AT91_REG PIO_PUER; /* Pull-up Enable Register */
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AT91_REG PIO_PUSR; /* Pad Pull-up Status Register */
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AT91_REG Reserved4[1];
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AT91_REG PIO_ASR; /* Select A Register */
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AT91_REG PIO_BSR; /* Select B Register */
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AT91_REG PIO_ABSR; /* AB Select Status Register */
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AT91_REG Reserved5[9];
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AT91_REG PIO_OWER; /* Output Write Enable Register */
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AT91_REG PIO_OWDR; /* Output Write Disable Register */
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AT91_REG PIO_OWSR; /* Output Write Status Register */
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} AT91S_PIO, *AT91PS_PIO;
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void pio_out(AT91S_PIO * pio, int mask, unsigned long val, int opcion);
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int pio_in(AT91S_PIO * pio, int mask);
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AT91S_PIO *pio_map(unsigned int piobase);
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void pio_enable(AT91S_PIO * pio, int mask);
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void pio_output_enable(AT91S_PIO * pio, int mask);
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void pio_input_enable(AT91S_PIO * pio, int mask);
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void pio_disable_irq(AT91S_PIO * pio, int mask);
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void pio_disable_multiple_driver(AT91S_PIO * pio, int mask);
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void pio_disable_pull_ups(AT91S_PIO * pio, int mask);
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void pio_synchronous_data_output(AT91S_PIO * pio, int mask);
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#endif
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