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// *****************************************************************************
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// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
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// *****************************************************************************
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#ifndef ADC_AT91_H
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#define ADC_AT91_H
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#define MAP_SIZE 4096Ul
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#define MAP_MASK (MAP_SIZE - 1)
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#define ADC_BASE 0xFFFE0000
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// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
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#define ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
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#define ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
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// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
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#define ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
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#define ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
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#define ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
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#define ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
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#define ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
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#define ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
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#define ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
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#define ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
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#define ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
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#define ADC_RES_10BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
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#define ADC_RES_8BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
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#define ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
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#define ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
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#define ADC_PRESCAL ((unsigned int) 0x31 << 2) // (ADC) Prescaler rate selection
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#define ADC_STARTUP ((unsigned int) 0x00 << 2) // (ADC) Startup Time
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#define ADC_SHTIM ((unsigned int) 0x01 << 9) // (ADC) Sample & Hold Time
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// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
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#define ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
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#define ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
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#define ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
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#define ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
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/*Anadido por DCordova*/
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// -------- ADC_CHSR : (ADC Offset: 0x10) ADC Channel Status Register --------
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#define ADC_CHSR0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
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#define ADC_CHSR1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
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#define ADC_CHSR2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
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#define ADC_CHSR3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
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/*Anadido por DCordova*/
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// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
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// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
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// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
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#define MASK_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
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#define MASK_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
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#define MASK_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
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#define MASK_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
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#define MASK_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
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#define MASK_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
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#define MASK_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
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#define MASK_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
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#define MASK_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
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#define MASK_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
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// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
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#define ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
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#define ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
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#define ADC_DISABLE_INTERRUP ((unsigned int) 0x0F0F0F << 0) //(ADC) Disable all interrup
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typedef volatile unsigned int AT91_REG2;// Hardware register definition
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typedef struct _AT91S_ADC {
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AT91_REG2 ADC_CR; // ADC Control Register
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AT91_REG2 ADC_MR; // ADC Mode Register
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AT91_REG2 Reserved0[2]; //
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AT91_REG2 ADC_CHER; // ADC Channel Enable Register
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AT91_REG2 ADC_CHDR; // ADC Channel Disable Register
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AT91_REG2 ADC_CHSR; // ADC Channel Status Register
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AT91_REG2 ADC_SR; // ADC Status Register
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AT91_REG2 ADC_LCDR; // ADC Last Converted Data Register
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AT91_REG2 ADC_IER; // ADC Interrupt Enable Register
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AT91_REG2 ADC_IDR; // ADC Interrupt Disable Register
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AT91_REG2 ADC_IMR; // ADC Interrupt Mask Register
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AT91_REG2 ADC_CDR0; // ADC Channel Data Register 0
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AT91_REG2 ADC_CDR1; // ADC Channel Data Register 1
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AT91_REG2 ADC_CDR2; // ADC Channel Data Register 2
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AT91_REG2 ADC_CDR3; // ADC Channel Data Register 3
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AT91_REG2 ADC_CDR4; // ADC Channel Data Register 4
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AT91_REG2 ADC_CDR5; // ADC Channel Data Register 5
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AT91_REG2 ADC_CDR6; // ADC Channel Data Register 6
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AT91_REG2 ADC_CDR7; // ADC Channel Data Register 7
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AT91_REG2 Reserved1[44]; //
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AT91_REG2 ADC_RPR; // Receive Pointer Register
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AT91_REG2 ADC_RCR; // Receive Counter Register
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AT91_REG2 ADC_TPR; // Transmit Pointer Register
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AT91_REG2 ADC_TCR; // Transmit Counter Register
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AT91_REG2 ADC_RNPR; // Receive Next Pointer Register
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AT91_REG2 ADC_RNCR; // Receive Next Counter Register
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AT91_REG2 ADC_TNPR; // Transmit Next Pointer Register
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AT91_REG2 ADC_TNCR; // Transmit Next Counter Register
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AT91_REG2 ADC_PTCR; // PDC Transfer Control Register
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AT91_REG2 ADC_PTSR; // PDC Transfer Status Register
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} AT91S_ADC, *AT91PS_ADC;
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AT91S_ADC *adc_map(unsigned int adcbase);
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/**********************Aniadido por DCV*********/
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AT91S_ADC *adc_map1(unsigned int adcbase);
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/**********************Aniadido por DCV*********/
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void ADC_INIT(AT91S_ADC * adc);
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void ADC_RESET(AT91S_ADC * adc);
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void CONFIG_ADC(AT91S_ADC * adc,unsigned int REG_CONFIG);
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void ENABLE_CHANNEL(AT91S_ADC * adc,unsigned int CHANNEL);
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unsigned int STATUS_CHANNEL(AT91S_ADC * adc);
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unsigned int GET_ADC(AT91S_ADC * adc);
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unsigned int GET_ADC0(AT91S_ADC * adc);
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unsigned int GET_ADC1(AT91S_ADC * adc);
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unsigned int GET_ADC3(AT91S_ADC * adc);
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unsigned int ver_reg_mode(AT91S_ADC * adc);
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unsigned int GET_STATUS(AT91S_ADC * adc);
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#endif
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