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1 /*
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2 * Mensajes.h
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3 *
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4 * Created on: Nov 12, 2009
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5 * Author: redes
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6 */
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7
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8 #ifndef MENSAJES_H_
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9 #define MENSAJES_H_
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10
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11 void LOG_SERVIDOR(char *mensaje);
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12 void LOG_CLIENTE(char *mensaje);
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13 void ERROR_FATAL(char *mensaje);
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14 void ERROR(char *mensaje);
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15
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16
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17 #endif /* MENSAJES_H_ */ No newline at end of file
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1 // *****************************************************************************
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2 // SOFTWARE API DEFINITION FOR Analog to Digital Convertor
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3 // *****************************************************************************
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4
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5 #ifndef ADC_AT91_H
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6 #define ADC_AT91_H
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7
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8 #define MAP_SIZE 4096Ul
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9 #define MAP_MASK (MAP_SIZE - 1)
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10
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11 #define ADC_BASE 0xFFFE0000
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12
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13 // -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
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14 #define ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
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15 #define ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
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16 // -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
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17 #define ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
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18 #define ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
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19
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20 #define ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
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21 #define ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
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22 #define ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
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23 #define ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
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24 #define ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
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25 #define ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
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26 #define ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
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27
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28 #define ADC_RES_10BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
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29 #define ADC_RES_8BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
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30
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31 #define ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
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32 #define ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
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33
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34 #define ADC_PRESCAL ((unsigned int) 0x31 << 2) // (ADC) Prescaler rate selection
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35 #define ADC_STARTUP ((unsigned int) 0x00 << 2) // (ADC) Startup Time
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36 #define ADC_SHTIM ((unsigned int) 0x01 << 9) // (ADC) Sample & Hold Time
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37
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38 // -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
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39 #define ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
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40 #define ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
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41 #define ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
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42 #define ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
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43
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44 /*Anadido por DCordova*/
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45 // -------- ADC_CHSR : (ADC Offset: 0x10) ADC Channel Status Register --------
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46 #define ADC_CHSR0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
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47 #define ADC_CHSR1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
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48 #define ADC_CHSR2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
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49 #define ADC_CHSR3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
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50 /*Anadido por DCordova*/
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51
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52
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53 // -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
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54 // -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
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55 // -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
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56
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57 #define MASK_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
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58 #define MASK_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
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59 #define MASK_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
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60 #define MASK_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
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61 #define MASK_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
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62 #define MASK_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
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63 #define MASK_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
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64 #define MASK_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
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65 #define MASK_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
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66 #define MASK_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
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67
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68 // -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
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69 #define ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
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70 #define ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
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71 #define ADC_DISABLE_INTERRUP ((unsigned int) 0x0F0F0F << 0) //(ADC) Disable all interrup
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72
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73 typedef volatile unsigned int AT91_REG2;// Hardware register definition
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74
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75 typedef struct _AT91S_ADC {
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76 AT91_REG2 ADC_CR; // ADC Control Register
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77 AT91_REG2 ADC_MR; // ADC Mode Register
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78 AT91_REG2 Reserved0[2]; //
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79 AT91_REG2 ADC_CHER; // ADC Channel Enable Register
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80 AT91_REG2 ADC_CHDR; // ADC Channel Disable Register
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81 AT91_REG2 ADC_CHSR; // ADC Channel Status Register
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82 AT91_REG2 ADC_SR; // ADC Status Register
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83 AT91_REG2 ADC_LCDR; // ADC Last Converted Data Register
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84 AT91_REG2 ADC_IER; // ADC Interrupt Enable Register
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85 AT91_REG2 ADC_IDR; // ADC Interrupt Disable Register
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86 AT91_REG2 ADC_IMR; // ADC Interrupt Mask Register
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87 AT91_REG2 ADC_CDR0; // ADC Channel Data Register 0
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88 AT91_REG2 ADC_CDR1; // ADC Channel Data Register 1
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89 AT91_REG2 ADC_CDR2; // ADC Channel Data Register 2
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90 AT91_REG2 ADC_CDR3; // ADC Channel Data Register 3
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91 AT91_REG2 ADC_CDR4; // ADC Channel Data Register 4
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92 AT91_REG2 ADC_CDR5; // ADC Channel Data Register 5
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93 AT91_REG2 ADC_CDR6; // ADC Channel Data Register 6
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94 AT91_REG2 ADC_CDR7; // ADC Channel Data Register 7
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95 AT91_REG2 Reserved1[44]; //
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96 AT91_REG2 ADC_RPR; // Receive Pointer Register
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97 AT91_REG2 ADC_RCR; // Receive Counter Register
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98 AT91_REG2 ADC_TPR; // Transmit Pointer Register
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99 AT91_REG2 ADC_TCR; // Transmit Counter Register
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100 AT91_REG2 ADC_RNPR; // Receive Next Pointer Register
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101 AT91_REG2 ADC_RNCR; // Receive Next Counter Register
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102 AT91_REG2 ADC_TNPR; // Transmit Next Pointer Register
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103 AT91_REG2 ADC_TNCR; // Transmit Next Counter Register
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104 AT91_REG2 ADC_PTCR; // PDC Transfer Control Register
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105 AT91_REG2 ADC_PTSR; // PDC Transfer Status Register
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106 } AT91S_ADC, *AT91PS_ADC;
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107
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108 AT91S_ADC *adc_map(unsigned int adcbase);
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109 /**********************Aniadido por DCV*********/
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110 AT91S_ADC *adc_map1(unsigned int adcbase);
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111 /**********************Aniadido por DCV*********/
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112
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113 void ADC_INIT(AT91S_ADC * adc);
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114 void ADC_RESET(AT91S_ADC * adc);
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115 void CONFIG_ADC(AT91S_ADC * adc,unsigned int REG_CONFIG);
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116 void ENABLE_CHANNEL(AT91S_ADC * adc,unsigned int CHANNEL);
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117 unsigned int STATUS_CHANNEL(AT91S_ADC * adc);
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118 unsigned int GET_ADC(AT91S_ADC * adc);
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119 unsigned int GET_ADC0(AT91S_ADC * adc);
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120 unsigned int GET_ADC1(AT91S_ADC * adc);
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121 unsigned int GET_ADC3(AT91S_ADC * adc);
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122 unsigned int ver_reg_mode(AT91S_ADC * adc);
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123 unsigned int GET_STATUS(AT91S_ADC * adc);
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124 #endif No newline at end of file
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1 /*
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2 * This programmer uses AT91' GPIO lines
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3 *
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4 * 2006 by Carlos Camargo
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5 * 2007.May.10 Andres Calderon
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6 * 2009.Aug.26 Jose Francisco Quenta
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7 */
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8
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9 #ifndef ECB_AT91_H
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10 #define ECB_AT91_H
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11
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12
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13 #define MAP_SIZE 4096Ul
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14 #define MAP_MASK (MAP_SIZE - 1)
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15
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16 #define PIOA_BASE 0xFFFFF400
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17 #define PIOB_BASE 0xFFFFF600
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18 #define PIOC_BASE 0xFFFFF800
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19 #define PIOD_BASE 0xFFFFFA00
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20
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21 #define PB0 (1 << 0)
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22 #define PB1 (1 << 1)
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23 #define PB2 (1 << 2)
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24 #define PB3 (1 << 3)
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25 #define PB8 (1 << 8)
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26 #define PB9 (1 << 9)
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27 #define PB10 (1 << 10)
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28 #define PB11 (1 << 11)
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29 #define PB16 (1 << 16)
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30 #define PB17 (1 << 17)
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31 #define PB18 (1 << 18)
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32 #define PB19 (1 << 19)
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33 #define PB20 (1 << 20)
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34 #define PB21 (1 << 21)
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35 #define PB22 (1 << 22)
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36 #define PB23 (1 << 23)
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37 #define PB24 (1 << 24)
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38 #define PB25 (1 << 25)
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39 #define PB30 (1 << 30)
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40 #define PB31 (1 << 31)
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41
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42 #define PC0 (1 << 0)
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43 #define PC1 (1 << 1)
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44 #define PC4 (1 << 4)
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45 #define PC5 (1 << 5)
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46 #define PC6 (1 << 6)
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47 #define PC7 (1 << 7)
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48 #define PC8 (1 << 8)
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49 #define PC9 (1 << 9)
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50 #define PC10 (1 << 10)
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51 #define PC11 (1 << 11)
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52 #define PC16 (1 << 16)
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53 #define PC17 (1 << 17)
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54 #define PC18 (1 << 18)
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55 #define PC19 (1 << 19)
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56 #define PC20 (1 << 20)
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57 #define PC21 (1 << 21)
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58 #define PC22 (1 << 22)
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59 #define PC23 (1 << 23)
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60 #define PC24 (1 << 24)
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61 #define PC25 (1 << 25)
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62 #define PC26 (1 << 26)
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63 #define PC27 (1 << 27)
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64 #define PC28 (1 << 28)
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65 #define PC29 (1 << 29)
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66 #define PC30 (1 << 30)
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67 #define PC31 (1 << 31)
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68
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69
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70 typedef volatile unsigned int AT91_REG;
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71 /* Hardware register definition */
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72
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73 typedef struct _AT91S_PIO {
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74 AT91_REG PIO_PER; /* PIO Enable Register */
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75 AT91_REG PIO_PDR; /* PIO Disable Register */
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76 AT91_REG PIO_PSR; /* PIO Status Register */
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77 AT91_REG Reserved0[1];
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78 AT91_REG PIO_OER; /* Output Enable Register */
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79 AT91_REG PIO_ODR; /* Output Disable Registerr */
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80 AT91_REG PIO_OSR; /* Output Status Register */
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81 AT91_REG Reserved1[1];
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82 AT91_REG PIO_IFER; /* Input Filter Enable Register */
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83 AT91_REG PIO_IFDR; /* Input Filter Disable Register */
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84 AT91_REG PIO_IFSR; /* Input Filter Status Register */
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85 AT91_REG Reserved2[1];
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86 AT91_REG PIO_SODR; /* Set Output Data Register */
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87 AT91_REG PIO_CODR; /* Clear Output Data Register */
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88 AT91_REG PIO_ODSR; /* Output Data Status Register */
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89 AT91_REG PIO_PDSR; /* Pin Data Status Register */
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90 AT91_REG PIO_IER; /* Interrupt Enable Register */
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91 AT91_REG PIO_IDR; /* Interrupt Disable Register */
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92 AT91_REG PIO_IMR; /* Interrupt Mask Register */
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93 AT91_REG PIO_ISR; /* Interrupt Status Register */
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94 AT91_REG PIO_MDER; /* Multi-driver Enable Register */
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95 AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
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96 AT91_REG PIO_MDSR; /* Multi-driver Status Register */
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97 AT91_REG Reserved3[1];
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98 AT91_REG PIO_PUDR; /* Pull-up Disable Register */
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99 AT91_REG PIO_PUER; /* Pull-up Enable Register */
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100 AT91_REG PIO_PUSR; /* Pad Pull-up Status Register */
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101 AT91_REG Reserved4[1];
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102 AT91_REG PIO_ASR; /* Select A Register */
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103 AT91_REG PIO_BSR; /* Select B Register */
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104 AT91_REG PIO_ABSR; /* AB Select Status Register */
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105 AT91_REG Reserved5[9];
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106 AT91_REG PIO_OWER; /* Output Write Enable Register */
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107 AT91_REG PIO_OWDR; /* Output Write Disable Register */
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108 AT91_REG PIO_OWSR; /* Output Write Status Register */
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109 } AT91S_PIO, *AT91PS_PIO;
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110
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111 void pio_out(AT91S_PIO * pio, int mask, unsigned long val, int opcion);
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112
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113 int pio_in(AT91S_PIO * pio, int mask);
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114
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115 AT91S_PIO *pio_map(unsigned int piobase);
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116
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117 void pio_enable(AT91S_PIO * pio, int mask);
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118
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119 void pio_output_enable(AT91S_PIO * pio, int mask);
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120
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121 void pio_input_enable(AT91S_PIO * pio, int mask);
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122
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123 void pio_disable_irq(AT91S_PIO * pio, int mask);
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124
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125 void pio_disable_multiple_driver(AT91S_PIO * pio, int mask);
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126
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127 void pio_disable_pull_ups(AT91S_PIO * pio, int mask);
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128
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129 void pio_synchronous_data_output(AT91S_PIO * pio, int mask);
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130
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131 //funciones agregadas para la realizar el estado de algunos registros:
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132 int ver_registro(AT91S_PIO * pio);
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133 void pin_adc_enable(AT91S_PIO * pio, int mask);
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134 void periferico_a(AT91S_PIO * pio, int mask);
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135 int ver_periferico(AT91S_PIO * pio);
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136
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137 #endif No newline at end of file
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1 // *****************************************************************************
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2 // SOFTWARE API DEFINITION FOR Power Management Controler
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3 // *****************************************************************************
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4 #ifndef SYSCLOCK_AT91_H
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5 #define SYSCLOCK_AT91_H
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6
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7 #define MAP_SIZE 4096Ul
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8 #define MAP_MASK (MAP_SIZE - 1)
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9
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10 #define CLOCK_BASE 0xFFFFFC00
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11 // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
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12 #define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
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13 #define AT91C_PMC_UHP ((unsigned int) 0x1 << 6) // (PMC) USB Host Port Clock
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14 #define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
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15 #define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
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16 #define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
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17 #define AT91C_PMC_HCK0 ((unsigned int) 0x1 << 16) // (PMC) AHB UHP Clock Output
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18 #define AT91C_PMC_HCK1 ((unsigned int) 0x1 << 17) // (PMC) AHB LCDC Clock Output
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19 // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
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20 // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
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21 // -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
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22 // -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
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23 // -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register --------
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24 // -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register --------
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25 // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
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26 #define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
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27 #define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
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28 #define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
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29 #define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) // (PMC) Clock from PLL A is selected
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30 #define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL B is selected
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31 #define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
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32 #define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
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33 #define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
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34 #define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
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35 #define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
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36 #define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
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37 #define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
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38 #define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
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39 #define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) // (PMC) Master Clock Division
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40 #define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) // (PMC) The master clock and the processor clock are the same
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41 #define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock
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42 #define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) // (PMC) The processor clock is four times faster than the master clock
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43 // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
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44 // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
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45 #define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
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46 #define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask
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47 #define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask
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48 #define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask
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49 #define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
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50 #define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
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51 // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
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52 // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
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53 // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
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54
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55 typedef volatile unsigned int AT91_REG3;// Hardware register definition
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56 typedef struct _AT91S_PMC {
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57 AT91_REG3 PMC_SCER; // System Clock Enable Register
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58 AT91_REG3 PMC_SCDR; // System Clock Disable Register
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59 AT91_REG3 PMC_SCSR; // System Clock Status Register
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60 AT91_REG3 Reserved0[1]; //
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61 AT91_REG3 PMC_PCER; // Peripheral Clock Enable Register
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62 AT91_REG3 PMC_PCDR; // Peripheral Clock Disable Register
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63 AT91_REG3 PMC_PCSR; // Peripheral Clock Status Register
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64 AT91_REG3 Reserved1[1]; //
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65 AT91_REG3 PMC_MOR; // Main Oscillator Register
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66 AT91_REG3 PMC_MCFR; // Main Clock Frequency Register
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67 AT91_REG3 PMC_PLLAR; // PLL A Register
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68 AT91_REG3 PMC_PLLBR; // PLL B Register
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69 AT91_REG3 PMC_MCKR; // Master Clock Register
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70 AT91_REG3 Reserved2[3]; //
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71 AT91_REG3 PMC_PCKR[8]; // Programmable Clock Register
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72 AT91_REG3 PMC_IER; // Interrupt Enable Register
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73 AT91_REG3 PMC_IDR; // Interrupt Disable Register
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74 AT91_REG3 PMC_SR; // Status Register
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75 AT91_REG3 PMC_IMR; // Interrupt Mask Register
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76 } AT91S_PMC, *AT91PS_PMC;
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77
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78 //Funciones:
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79 AT91S_PMC *clock_map(unsigned int clockbase);
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80 void enable_clock_adc(AT91S_PMC * clock);
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81 unsigned int status_clock_adc(AT91S_PMC * clock);
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82 #endif
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83 No newline at end of file
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1 /*
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2 * Mensajes.c
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3 *
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4 * Created on: Nov 12, 2009
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5 * Author: Jose Francisco Quenta
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6 */
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7
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8 #include <stdio.h>
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9 #include <stdlib.h>
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10
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11 /*
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12 * Imprime mensajes del servidor
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13 */
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14 void LOG_SERVIDOR(char *mensaje){
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15 printf("SERVIDOR: %s\n",mensaje);
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16 }
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17
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18 /*
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19 * Imprime mensajes del cliente
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20 */
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21 void LOG_CLIENTE(char *mensaje){
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22 printf("CLIENTE: %s\n",mensaje);
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23 }
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24
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25 /*
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26 * Error no fatal, permite la continuación del programa
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27 */
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28 void ERROR(char *mensaje){
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29 fprintf(stderr, "ERROR. %s\n", mensaje);
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30 }
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31
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32 /*
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33 * Error fatal, aborta la ejecución del programa con código de salida de error
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34 */
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35 void ERROR_FATAL(char *mensaje){
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36 fprintf(stderr, "ERROR FATAL. %s\n", mensaje);
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37 exit(EXIT_FAILURE);
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38 }
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39 No newline at end of file
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1 /*
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2 * This programmer uses AT91' ADC Module
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3 *
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4 * 2010 by Ricardo V. Rojas Quispe
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5 */
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6
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7 #include <stdint.h>
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8 #include <stdlib.h>
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9 #include <stdio.h>
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10 #include <unistd.h>
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11
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12 #include <sys/types.h>
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13 #include <sys/stat.h>
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14 #include <sys/mman.h>
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15 #include <fcntl.h>
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16
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17 #include "./Librerias/at91adc.h"
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18
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19 AT91S_ADC *adc_map(unsigned int adcbase){
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20 int fd;
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21 void *base;
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22
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23 AT91S_ADC *adc;
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24
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25 off_t addr = adcbase;
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26
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27 if ((fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1) {
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28 fprintf(stderr, "Cannot open /dev/mem.\n");
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29 exit(EXIT_FAILURE);
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30 }
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31
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32
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33 base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, addr & ~MAP_MASK);
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34
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35 if (base == (void *) -1) {
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36 fprintf(stderr, "Cannot open /dev/mem.\n");
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37 exit(EXIT_FAILURE);
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38 }
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39
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40
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41 adc = base + (addr & MAP_MASK);
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42
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43 return adc;
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44 }
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45 /**********************Anadido por DCV*ini********/
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46 AT91S_ADC *adc_map1(unsigned int adcbase){
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47 int fd;
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48 void *base;
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49
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50 AT91S_ADC *adc;
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51
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52 off_t addr = adcbase;
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53
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54 if ((fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1) {
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55 //fprintf(stderr, "Cannot open /dev/mem.\n");
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56 exit(EXIT_FAILURE);
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57 }
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58
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59 base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, addr & ~MAP_MASK);
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60
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61 if (base == (void *) -1) {
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62 //fprintf(stderr, "Cannot open /dev/mem.\n");
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63 exit(EXIT_FAILURE);
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64 }
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65
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66 adc = base + (addr & MAP_MASK);
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67
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68 return adc;
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69 }
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70
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71 /*********************Anadido por DCV*fin**********/
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72 void ADC_INIT(AT91S_ADC * adc){
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73 //Incia conversion ADC
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74 adc->ADC_CR = ADC_START;
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75 }
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76
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77 void ADC_RESET(AT91S_ADC * adc){
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78 //Reset de ADC
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79 adc->ADC_CR = ADC_SWRST;
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80 }
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81 void CONFIG_ADC(AT91S_ADC * adc,unsigned int REG_CONFIG){
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82 //configura ADC
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83 adc->ADC_MR = REG_CONFIG;
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84 adc->ADC_IDR = ADC_DISABLE_INTERRUP;
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85 }
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86 void ENABLE_CHANNEL(AT91S_ADC * adc,unsigned int CHANNEL){
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87 //Habilita canal selecconado y deshabilita el resto
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88 adc->ADC_CHER = CHANNEL & 0x0F;
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89 adc->ADC_CHDR = ~CHANNEL & 0x0F;
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90 }
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91 unsigned int STATUS_CHANNEL(AT91S_ADC * adc){
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92 //Retorna el estado del canal habilitado
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93 return (adc->ADC_CHSR);
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94 }
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95 unsigned int GET_ADC(AT91S_ADC * adc){
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96 //unsigned int valor=1;
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97 //Retorna el valor de ADC (resolucion de 10BIT)
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98 while(1){
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99 if ((adc-> ADC_SR & MASK_DRDY) == MASK_DRDY)
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100 break;
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101 }
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102 return (adc->ADC_LCDR & ADC_LDATA);
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103 }
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104 unsigned int GET_STATUS(AT91S_ADC * adc){
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105 //Retorna el estado del ADC (registro)
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106 return (adc->ADC_SR);
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107 }
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108 unsigned int GET_ADC0(AT91S_ADC * adc){
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109 //Retorna el valor de la conversion del canal 0
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110 while(1){
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111 if ((adc->ADC_SR & MASK_EOC0) == MASK_EOC0)
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112 break;
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113 }
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114 return (adc->ADC_CDR0 & ADC_LDATA);
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115 }
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116 unsigned int GET_ADC1(AT91S_ADC * adc){
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117 //Retorna el valor de la conversion del canal 1
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118 while(1){
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119 if ((adc->ADC_SR & MASK_EOC1) == MASK_EOC1)
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120 break;
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121 }
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122 return (adc->ADC_CDR1 & ADC_LDATA);
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123 }
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124 unsigned int GET_ADC3(AT91S_ADC * adc){
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125 unsigned int valor=1;
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126 //Retorna el valor de ADC (resolucion de 10BIT)
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127 while(valor){
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128 if ((adc-> ADC_SR) & 0x10000)
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129 valor = 0;
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130 else
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131 valor = 1;
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132 }
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133 return (adc->ADC_CDR1 & ADC_DATA);
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134 }
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135 unsigned int ver_reg_mode(AT91S_ADC * adc){
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136 //retorna el valor del ADC_MR
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137 return (adc->ADC_MR);
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138 } No newline at end of file
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1 /*
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2 * This programmer uses AT91' GPIO lines
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3 *
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4 * 2006 by Carlos Camargo
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5 * 2007.May.10 Andres Calderon
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6 * 2009.Aug.26 Jose Francisco Quenta
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7 */
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8
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9 #include <stdint.h>
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10 #include <stdlib.h>
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11 #include <stdio.h>
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12 #include <unistd.h>
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13
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14
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15 #include <sys/types.h>
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16 #include <sys/stat.h>
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17 #include <sys/mman.h>
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18 #include <fcntl.h>
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19
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20 #include "./Librerias/at91gpio.h"
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21
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22 void pio_out(AT91S_PIO * pio, int mask, unsigned long val, int opcion)
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23 {
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24 if (opcion == 1)
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25 pio->PIO_SODR = mask & val;
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26 else
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27 pio->PIO_CODR = mask & val;
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28 }
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29
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30
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31 int pio_in(AT91S_PIO * pio, int mask)
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32 {
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33 return (pio->PIO_PDSR & mask);
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34 }
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35
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36
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37 AT91S_PIO *pio_map(unsigned int piobase)
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38 {
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39 int fd;
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40 void *base;
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41
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42 AT91S_PIO *pio;
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43
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44 off_t addr = piobase;
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45
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46 if ((fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1) {
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47 fprintf(stderr, "Cannot open /dev/mem.\n");
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48 exit(EXIT_FAILURE);
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49 }
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50
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51 fprintf(stderr, "/dev/mem opened.\n");
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52
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53 base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, addr & ~MAP_MASK);
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54
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55 if (base == (void *) -1) {
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56 fprintf(stderr, "Cannot open /dev/mem.\n");
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57 exit(EXIT_FAILURE);
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58 }
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59
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60 fprintf(stderr, "Memory mapped at address %p.\n", base);
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61
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62 pio = base + (addr & MAP_MASK);
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63
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64 return pio;
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65 }
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66
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67
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68 void pio_enable(AT91S_PIO * pio, int mask)
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69 {
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70 pio->PIO_PER = mask; /* Enable PIO */
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71 }
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72
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73 void pio_output_enable(AT91S_PIO * pio, int mask)
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74 {
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75 pio->PIO_OER = mask; /* Set TDI, TMS and TCK as outputs */
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76 }
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77
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78 void pio_input_enable(AT91S_PIO * pio, int mask)
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79 {
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80 pio->PIO_ODR = mask; /* Set TDO as input */
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81 pio->PIO_IFER = mask; /* Enable Input Filter */
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82 }
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83
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84 void pio_disable_irq(AT91S_PIO * pio, int mask)
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85 {
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86 pio->PIO_IDR = mask; /* Disable pin interrupts */
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87 }
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88
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89 void pio_disable_multiple_driver(AT91S_PIO * pio, int mask)
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90 {
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91 pio->PIO_MDDR = mask; /* Disable Multiple Diver */
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92 }
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93
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94 void pio_disable_pull_ups(AT91S_PIO * pio, int mask)
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95 {
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96 pio->PIO_PUDR = mask; /* Disable Pull-Ups */
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97 }
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98
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99 void pio_synchronous_data_output(AT91S_PIO * pio, int mask)
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100 {
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101 pio->PIO_OWDR = mask; /* Synchronous Data Output Write in PIO_ */
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102 }
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103
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104 //Nuevas funciones:
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105 int ver_registro(AT91S_PIO * pio){
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106 return (pio->PIO_PSR);
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107 }
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108 //Habilitar pines para usar con ADC
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109 void pin_adc_enable(AT91S_PIO * pio, int mask){
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110 pio->PIO_PDR = mask;
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111 }
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112 //selecciona para el periferico A
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113 void periferico_a(AT91S_PIO * pio, int mask){
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114 pio->PIO_ASR = mask;
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115 }
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116 //Retorna cero si esta en el perifierico A y 1 si est aen el periferico B
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117 int ver_periferico(AT91S_PIO * pio){
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118 return (pio->PIO_ABSR & 0x01);
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119 } No newline at end of file
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1 /*
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2 * This programmer uses AT91' System clock
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3 *
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4 * 2010 by Ricardo V. Rojas Quispe
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5 */
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6
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7 #include <stdint.h>
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8 #include <stdlib.h>
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9 #include <stdio.h>
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10 #include <unistd.h>
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11
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12 #include <sys/types.h>
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13 #include <sys/stat.h>
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14 #include <sys/mman.h>
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15 #include <fcntl.h>
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16
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17 #include "./Librerias/at91sysclock.h"
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18
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19 //Mapeando los registro en memoria:
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20 AT91S_PMC *clock_map(unsigned int clockbase){
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21 int fd;
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22 void *base;
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23
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24 AT91S_PMC *clock;
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25
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26 off_t addr = clockbase;
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27
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28 if ((fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1) {
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29 fprintf(stderr, "Cannot open /dev/mem.\n");
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30 exit(EXIT_FAILURE);
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31 }
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32
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33 //fprintf(stderr, "/dev/mem opened.\n");
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34
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35 base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, addr & ~MAP_MASK);
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36
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37 if (base == (void *) -1) {
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38 fprintf(stderr, "Cannot open /dev/mem.\n");
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39 exit(EXIT_FAILURE);
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40 }
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41
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42 //fprintf(stderr, "Memory mapped at address %p.\n", base);
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43
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44 clock = base + (addr & MAP_MASK);
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45
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46 return clock;
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47 }
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48 //Habilitamos el clock de ADC
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49 void enable_clock_adc(AT91S_PMC * clock){
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50 clock->PMC_PCER=0x20;
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51 }
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52 //Leemos el registro de estado de clock para perifericos
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53 unsigned int status_clock_adc(AT91S_PMC * clock){
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54 return (clock->PMC_PCSR);
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55 } No newline at end of file
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@@ -25,9 +25,14
25 25 #include <netinet/in.h> No newline at end of file
26 26 #include <arpa/inet.h> No newline at end of file
27 27 #include <netdb.h>
28 No newline at end of file
28
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29 No newline at end of file
29 #include "./Librerias/AT91gpio_Funciones.h"
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30 No newline at end of file
30 #include "./Librerias/Mensajes.h" No newline at end of file
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31 #include "./Librerias/at91gpio.h"
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32 //#include "./Librerias/Mensajes.h"
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33 #include "./Librerias/at91adc.h"
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34 //clock
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35 #include "./Librerias/at91sysclock.h" No newline at end of file
31 36 No newline at end of file
32 37 #define PUERTO_SERVIDOR 5500 No newline at end of file
33 38 #define TAM_BUFFER 1024 No newline at end of file
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