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1 /*
2 * Mensajes.h
3 *
4 * Created on: Nov 12, 2009
5 * Author: redes
6 */
7
8 #ifndef MENSAJES_H_
9 #define MENSAJES_H_
10
11 void LOG_SERVIDOR(char *mensaje);
12 void LOG_CLIENTE(char *mensaje);
13 void ERROR_FATAL(char *mensaje);
14 void ERROR(char *mensaje);
15
16
17 #endif /* MENSAJES_H_ */
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1 // *****************************************************************************
2 // SOFTWARE API DEFINITION FOR Analog to Digital Convertor
3 // *****************************************************************************
4
5 #ifndef ADC_AT91_H
6 #define ADC_AT91_H
7
8 #define MAP_SIZE 4096Ul
9 #define MAP_MASK (MAP_SIZE - 1)
10
11 #define ADC_BASE 0xFFFE0000
12
13 // -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
14 #define ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
15 #define ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
16 // -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
17 #define ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
18 #define ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
19
20 #define ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
21 #define ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
22 #define ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
23 #define ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
24 #define ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
25 #define ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
26 #define ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
27
28 #define ADC_RES_10BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
29 #define ADC_RES_8BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
30
31 #define ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
32 #define ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
33
34 #define ADC_PRESCAL ((unsigned int) 0x31 << 2) // (ADC) Prescaler rate selection
35 #define ADC_STARTUP ((unsigned int) 0x00 << 2) // (ADC) Startup Time
36 #define ADC_SHTIM ((unsigned int) 0x01 << 9) // (ADC) Sample & Hold Time
37
38 // -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
39 #define ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
40 #define ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
41 #define ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
42 #define ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
43
44 /*Anadido por DCordova*/
45 // -------- ADC_CHSR : (ADC Offset: 0x10) ADC Channel Status Register --------
46 #define ADC_CHSR0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
47 #define ADC_CHSR1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
48 #define ADC_CHSR2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
49 #define ADC_CHSR3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
50 /*Anadido por DCordova*/
51
52
53 // -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
54 // -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
55 // -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
56
57 #define MASK_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
58 #define MASK_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
59 #define MASK_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
60 #define MASK_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
61 #define MASK_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
62 #define MASK_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
63 #define MASK_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
64 #define MASK_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
65 #define MASK_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
66 #define MASK_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
67
68 // -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
69 #define ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
70 #define ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
71 #define ADC_DISABLE_INTERRUP ((unsigned int) 0x0F0F0F << 0) //(ADC) Disable all interrup
72
73 typedef volatile unsigned int AT91_REG2;// Hardware register definition
74
75 typedef struct _AT91S_ADC {
76 AT91_REG2 ADC_CR; // ADC Control Register
77 AT91_REG2 ADC_MR; // ADC Mode Register
78 AT91_REG2 Reserved0[2]; //
79 AT91_REG2 ADC_CHER; // ADC Channel Enable Register
80 AT91_REG2 ADC_CHDR; // ADC Channel Disable Register
81 AT91_REG2 ADC_CHSR; // ADC Channel Status Register
82 AT91_REG2 ADC_SR; // ADC Status Register
83 AT91_REG2 ADC_LCDR; // ADC Last Converted Data Register
84 AT91_REG2 ADC_IER; // ADC Interrupt Enable Register
85 AT91_REG2 ADC_IDR; // ADC Interrupt Disable Register
86 AT91_REG2 ADC_IMR; // ADC Interrupt Mask Register
87 AT91_REG2 ADC_CDR0; // ADC Channel Data Register 0
88 AT91_REG2 ADC_CDR1; // ADC Channel Data Register 1
89 AT91_REG2 ADC_CDR2; // ADC Channel Data Register 2
90 AT91_REG2 ADC_CDR3; // ADC Channel Data Register 3
91 AT91_REG2 ADC_CDR4; // ADC Channel Data Register 4
92 AT91_REG2 ADC_CDR5; // ADC Channel Data Register 5
93 AT91_REG2 ADC_CDR6; // ADC Channel Data Register 6
94 AT91_REG2 ADC_CDR7; // ADC Channel Data Register 7
95 AT91_REG2 Reserved1[44]; //
96 AT91_REG2 ADC_RPR; // Receive Pointer Register
97 AT91_REG2 ADC_RCR; // Receive Counter Register
98 AT91_REG2 ADC_TPR; // Transmit Pointer Register
99 AT91_REG2 ADC_TCR; // Transmit Counter Register
100 AT91_REG2 ADC_RNPR; // Receive Next Pointer Register
101 AT91_REG2 ADC_RNCR; // Receive Next Counter Register
102 AT91_REG2 ADC_TNPR; // Transmit Next Pointer Register
103 AT91_REG2 ADC_TNCR; // Transmit Next Counter Register
104 AT91_REG2 ADC_PTCR; // PDC Transfer Control Register
105 AT91_REG2 ADC_PTSR; // PDC Transfer Status Register
106 } AT91S_ADC, *AT91PS_ADC;
107
108 AT91S_ADC *adc_map(unsigned int adcbase);
109 /**********************Aniadido por DCV*********/
110 AT91S_ADC *adc_map1(unsigned int adcbase);
111 /**********************Aniadido por DCV*********/
112
113 void ADC_INIT(AT91S_ADC * adc);
114 void ADC_RESET(AT91S_ADC * adc);
115 void CONFIG_ADC(AT91S_ADC * adc,unsigned int REG_CONFIG);
116 void ENABLE_CHANNEL(AT91S_ADC * adc,unsigned int CHANNEL);
117 unsigned int STATUS_CHANNEL(AT91S_ADC * adc);
118 unsigned int GET_ADC(AT91S_ADC * adc);
119 unsigned int GET_ADC0(AT91S_ADC * adc);
120 unsigned int GET_ADC1(AT91S_ADC * adc);
121 unsigned int GET_ADC3(AT91S_ADC * adc);
122 unsigned int ver_reg_mode(AT91S_ADC * adc);
123 unsigned int GET_STATUS(AT91S_ADC * adc);
124 #endif
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1 /*
2 * This programmer uses AT91' GPIO lines
3 *
4 * 2006 by Carlos Camargo
5 * 2007.May.10 Andres Calderon
6 * 2009.Aug.26 Jose Francisco Quenta
7 */
8
9 #ifndef ECB_AT91_H
10 #define ECB_AT91_H
11
12
13 #define MAP_SIZE 4096Ul
14 #define MAP_MASK (MAP_SIZE - 1)
15
16 #define PIOA_BASE 0xFFFFF400
17 #define PIOB_BASE 0xFFFFF600
18 #define PIOC_BASE 0xFFFFF800
19 #define PIOD_BASE 0xFFFFFA00
20
21 #define PB0 (1 << 0)
22 #define PB1 (1 << 1)
23 #define PB2 (1 << 2)
24 #define PB3 (1 << 3)
25 #define PB8 (1 << 8)
26 #define PB9 (1 << 9)
27 #define PB10 (1 << 10)
28 #define PB11 (1 << 11)
29 #define PB16 (1 << 16)
30 #define PB17 (1 << 17)
31 #define PB18 (1 << 18)
32 #define PB19 (1 << 19)
33 #define PB20 (1 << 20)
34 #define PB21 (1 << 21)
35 #define PB22 (1 << 22)
36 #define PB23 (1 << 23)
37 #define PB24 (1 << 24)
38 #define PB25 (1 << 25)
39 #define PB30 (1 << 30)
40 #define PB31 (1 << 31)
41
42 #define PC0 (1 << 0)
43 #define PC1 (1 << 1)
44 #define PC4 (1 << 4)
45 #define PC5 (1 << 5)
46 #define PC6 (1 << 6)
47 #define PC7 (1 << 7)
48 #define PC8 (1 << 8)
49 #define PC9 (1 << 9)
50 #define PC10 (1 << 10)
51 #define PC11 (1 << 11)
52 #define PC16 (1 << 16)
53 #define PC17 (1 << 17)
54 #define PC18 (1 << 18)
55 #define PC19 (1 << 19)
56 #define PC20 (1 << 20)
57 #define PC21 (1 << 21)
58 #define PC22 (1 << 22)
59 #define PC23 (1 << 23)
60 #define PC24 (1 << 24)
61 #define PC25 (1 << 25)
62 #define PC26 (1 << 26)
63 #define PC27 (1 << 27)
64 #define PC28 (1 << 28)
65 #define PC29 (1 << 29)
66 #define PC30 (1 << 30)
67 #define PC31 (1 << 31)
68
69
70 typedef volatile unsigned int AT91_REG;
71 /* Hardware register definition */
72
73 typedef struct _AT91S_PIO {
74 AT91_REG PIO_PER; /* PIO Enable Register */
75 AT91_REG PIO_PDR; /* PIO Disable Register */
76 AT91_REG PIO_PSR; /* PIO Status Register */
77 AT91_REG Reserved0[1];
78 AT91_REG PIO_OER; /* Output Enable Register */
79 AT91_REG PIO_ODR; /* Output Disable Registerr */
80 AT91_REG PIO_OSR; /* Output Status Register */
81 AT91_REG Reserved1[1];
82 AT91_REG PIO_IFER; /* Input Filter Enable Register */
83 AT91_REG PIO_IFDR; /* Input Filter Disable Register */
84 AT91_REG PIO_IFSR; /* Input Filter Status Register */
85 AT91_REG Reserved2[1];
86 AT91_REG PIO_SODR; /* Set Output Data Register */
87 AT91_REG PIO_CODR; /* Clear Output Data Register */
88 AT91_REG PIO_ODSR; /* Output Data Status Register */
89 AT91_REG PIO_PDSR; /* Pin Data Status Register */
90 AT91_REG PIO_IER; /* Interrupt Enable Register */
91 AT91_REG PIO_IDR; /* Interrupt Disable Register */
92 AT91_REG PIO_IMR; /* Interrupt Mask Register */
93 AT91_REG PIO_ISR; /* Interrupt Status Register */
94 AT91_REG PIO_MDER; /* Multi-driver Enable Register */
95 AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
96 AT91_REG PIO_MDSR; /* Multi-driver Status Register */
97 AT91_REG Reserved3[1];
98 AT91_REG PIO_PUDR; /* Pull-up Disable Register */
99 AT91_REG PIO_PUER; /* Pull-up Enable Register */
100 AT91_REG PIO_PUSR; /* Pad Pull-up Status Register */
101 AT91_REG Reserved4[1];
102 AT91_REG PIO_ASR; /* Select A Register */
103 AT91_REG PIO_BSR; /* Select B Register */
104 AT91_REG PIO_ABSR; /* AB Select Status Register */
105 AT91_REG Reserved5[9];
106 AT91_REG PIO_OWER; /* Output Write Enable Register */
107 AT91_REG PIO_OWDR; /* Output Write Disable Register */
108 AT91_REG PIO_OWSR; /* Output Write Status Register */
109 } AT91S_PIO, *AT91PS_PIO;
110
111 void pio_out(AT91S_PIO * pio, int mask, unsigned long val, int opcion);
112
113 int pio_in(AT91S_PIO * pio, int mask);
114
115 AT91S_PIO *pio_map(unsigned int piobase);
116
117 void pio_enable(AT91S_PIO * pio, int mask);
118
119 void pio_output_enable(AT91S_PIO * pio, int mask);
120
121 void pio_input_enable(AT91S_PIO * pio, int mask);
122
123 void pio_disable_irq(AT91S_PIO * pio, int mask);
124
125 void pio_disable_multiple_driver(AT91S_PIO * pio, int mask);
126
127 void pio_disable_pull_ups(AT91S_PIO * pio, int mask);
128
129 void pio_synchronous_data_output(AT91S_PIO * pio, int mask);
130
131 //funciones agregadas para la realizar el estado de algunos registros:
132 int ver_registro(AT91S_PIO * pio);
133 void pin_adc_enable(AT91S_PIO * pio, int mask);
134 void periferico_a(AT91S_PIO * pio, int mask);
135 int ver_periferico(AT91S_PIO * pio);
136
137 #endif
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1 // *****************************************************************************
2 // SOFTWARE API DEFINITION FOR Power Management Controler
3 // *****************************************************************************
4 #ifndef SYSCLOCK_AT91_H
5 #define SYSCLOCK_AT91_H
6
7 #define MAP_SIZE 4096Ul
8 #define MAP_MASK (MAP_SIZE - 1)
9
10 #define CLOCK_BASE 0xFFFFFC00
11 // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
12 #define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
13 #define AT91C_PMC_UHP ((unsigned int) 0x1 << 6) // (PMC) USB Host Port Clock
14 #define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
15 #define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
16 #define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
17 #define AT91C_PMC_HCK0 ((unsigned int) 0x1 << 16) // (PMC) AHB UHP Clock Output
18 #define AT91C_PMC_HCK1 ((unsigned int) 0x1 << 17) // (PMC) AHB LCDC Clock Output
19 // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
20 // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
21 // -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
22 // -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
23 // -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register --------
24 // -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register --------
25 // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
26 #define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
27 #define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
28 #define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
29 #define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) // (PMC) Clock from PLL A is selected
30 #define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL B is selected
31 #define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
32 #define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
33 #define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
34 #define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
35 #define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
36 #define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
37 #define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
38 #define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
39 #define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) // (PMC) Master Clock Division
40 #define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) // (PMC) The master clock and the processor clock are the same
41 #define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock
42 #define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) // (PMC) The processor clock is four times faster than the master clock
43 // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
44 // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
45 #define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
46 #define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask
47 #define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask
48 #define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask
49 #define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
50 #define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
51 // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
52 // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
53 // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
54
55 typedef volatile unsigned int AT91_REG3;// Hardware register definition
56 typedef struct _AT91S_PMC {
57 AT91_REG3 PMC_SCER; // System Clock Enable Register
58 AT91_REG3 PMC_SCDR; // System Clock Disable Register
59 AT91_REG3 PMC_SCSR; // System Clock Status Register
60 AT91_REG3 Reserved0[1]; //
61 AT91_REG3 PMC_PCER; // Peripheral Clock Enable Register
62 AT91_REG3 PMC_PCDR; // Peripheral Clock Disable Register
63 AT91_REG3 PMC_PCSR; // Peripheral Clock Status Register
64 AT91_REG3 Reserved1[1]; //
65 AT91_REG3 PMC_MOR; // Main Oscillator Register
66 AT91_REG3 PMC_MCFR; // Main Clock Frequency Register
67 AT91_REG3 PMC_PLLAR; // PLL A Register
68 AT91_REG3 PMC_PLLBR; // PLL B Register
69 AT91_REG3 PMC_MCKR; // Master Clock Register
70 AT91_REG3 Reserved2[3]; //
71 AT91_REG3 PMC_PCKR[8]; // Programmable Clock Register
72 AT91_REG3 PMC_IER; // Interrupt Enable Register
73 AT91_REG3 PMC_IDR; // Interrupt Disable Register
74 AT91_REG3 PMC_SR; // Status Register
75 AT91_REG3 PMC_IMR; // Interrupt Mask Register
76 } AT91S_PMC, *AT91PS_PMC;
77
78 //Funciones:
79 AT91S_PMC *clock_map(unsigned int clockbase);
80 void enable_clock_adc(AT91S_PMC * clock);
81 unsigned int status_clock_adc(AT91S_PMC * clock);
82 #endif
83
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1 /*
2 * Mensajes.c
3 *
4 * Created on: Nov 12, 2009
5 * Author: Jose Francisco Quenta
6 */
7
8 #include <stdio.h>
9 #include <stdlib.h>
10
11 /*
12 * Imprime mensajes del servidor
13 */
14 void LOG_SERVIDOR(char *mensaje){
15 printf("SERVIDOR: %s\n",mensaje);
16 }
17
18 /*
19 * Imprime mensajes del cliente
20 */
21 void LOG_CLIENTE(char *mensaje){
22 printf("CLIENTE: %s\n",mensaje);
23 }
24
25 /*
26 * Error no fatal, permite la continuación del programa
27 */
28 void ERROR(char *mensaje){
29 fprintf(stderr, "ERROR. %s\n", mensaje);
30 }
31
32 /*
33 * Error fatal, aborta la ejecución del programa con código de salida de error
34 */
35 void ERROR_FATAL(char *mensaje){
36 fprintf(stderr, "ERROR FATAL. %s\n", mensaje);
37 exit(EXIT_FAILURE);
38 }
39
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1 /*
2 * This programmer uses AT91' ADC Module
3 *
4 * 2010 by Ricardo V. Rojas Quispe
5 */
6
7 #include <stdint.h>
8 #include <stdlib.h>
9 #include <stdio.h>
10 #include <unistd.h>
11
12 #include <sys/types.h>
13 #include <sys/stat.h>
14 #include <sys/mman.h>
15 #include <fcntl.h>
16
17 #include "./Librerias/at91adc.h"
18
19 AT91S_ADC *adc_map(unsigned int adcbase){
20 int fd;
21 void *base;
22
23 AT91S_ADC *adc;
24
25 off_t addr = adcbase;
26
27 if ((fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1) {
28 fprintf(stderr, "Cannot open /dev/mem.\n");
29 exit(EXIT_FAILURE);
30 }
31
32
33 base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, addr & ~MAP_MASK);
34
35 if (base == (void *) -1) {
36 fprintf(stderr, "Cannot open /dev/mem.\n");
37 exit(EXIT_FAILURE);
38 }
39
40
41 adc = base + (addr & MAP_MASK);
42
43 return adc;
44 }
45 /**********************Anadido por DCV*ini********/
46 AT91S_ADC *adc_map1(unsigned int adcbase){
47 int fd;
48 void *base;
49
50 AT91S_ADC *adc;
51
52 off_t addr = adcbase;
53
54 if ((fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1) {
55 //fprintf(stderr, "Cannot open /dev/mem.\n");
56 exit(EXIT_FAILURE);
57 }
58
59 base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, addr & ~MAP_MASK);
60
61 if (base == (void *) -1) {
62 //fprintf(stderr, "Cannot open /dev/mem.\n");
63 exit(EXIT_FAILURE);
64 }
65
66 adc = base + (addr & MAP_MASK);
67
68 return adc;
69 }
70
71 /*********************Anadido por DCV*fin**********/
72 void ADC_INIT(AT91S_ADC * adc){
73 //Incia conversion ADC
74 adc->ADC_CR = ADC_START;
75 }
76
77 void ADC_RESET(AT91S_ADC * adc){
78 //Reset de ADC
79 adc->ADC_CR = ADC_SWRST;
80 }
81 void CONFIG_ADC(AT91S_ADC * adc,unsigned int REG_CONFIG){
82 //configura ADC
83 adc->ADC_MR = REG_CONFIG;
84 adc->ADC_IDR = ADC_DISABLE_INTERRUP;
85 }
86 void ENABLE_CHANNEL(AT91S_ADC * adc,unsigned int CHANNEL){
87 //Habilita canal selecconado y deshabilita el resto
88 adc->ADC_CHER = CHANNEL & 0x0F;
89 adc->ADC_CHDR = ~CHANNEL & 0x0F;
90 }
91 unsigned int STATUS_CHANNEL(AT91S_ADC * adc){
92 //Retorna el estado del canal habilitado
93 return (adc->ADC_CHSR);
94 }
95 unsigned int GET_ADC(AT91S_ADC * adc){
96 //unsigned int valor=1;
97 //Retorna el valor de ADC (resolucion de 10BIT)
98 while(1){
99 if ((adc-> ADC_SR & MASK_DRDY) == MASK_DRDY)
100 break;
101 }
102 return (adc->ADC_LCDR & ADC_LDATA);
103 }
104 unsigned int GET_STATUS(AT91S_ADC * adc){
105 //Retorna el estado del ADC (registro)
106 return (adc->ADC_SR);
107 }
108 unsigned int GET_ADC0(AT91S_ADC * adc){
109 //Retorna el valor de la conversion del canal 0
110 while(1){
111 if ((adc->ADC_SR & MASK_EOC0) == MASK_EOC0)
112 break;
113 }
114 return (adc->ADC_CDR0 & ADC_LDATA);
115 }
116 unsigned int GET_ADC1(AT91S_ADC * adc){
117 //Retorna el valor de la conversion del canal 1
118 while(1){
119 if ((adc->ADC_SR & MASK_EOC1) == MASK_EOC1)
120 break;
121 }
122 return (adc->ADC_CDR1 & ADC_LDATA);
123 }
124 unsigned int GET_ADC3(AT91S_ADC * adc){
125 unsigned int valor=1;
126 //Retorna el valor de ADC (resolucion de 10BIT)
127 while(valor){
128 if ((adc-> ADC_SR) & 0x10000)
129 valor = 0;
130 else
131 valor = 1;
132 }
133 return (adc->ADC_CDR1 & ADC_DATA);
134 }
135 unsigned int ver_reg_mode(AT91S_ADC * adc){
136 //retorna el valor del ADC_MR
137 return (adc->ADC_MR);
138 }
Show file before | Show file after | Hide comments
@@ -0,0 +1,119
1 /*
2 * This programmer uses AT91' GPIO lines
3 *
4 * 2006 by Carlos Camargo
5 * 2007.May.10 Andres Calderon
6 * 2009.Aug.26 Jose Francisco Quenta
7 */
8
9 #include <stdint.h>
10 #include <stdlib.h>
11 #include <stdio.h>
12 #include <unistd.h>
13
14
15 #include <sys/types.h>
16 #include <sys/stat.h>
17 #include <sys/mman.h>
18 #include <fcntl.h>
19
20 #include "./Librerias/at91gpio.h"
21
22 void pio_out(AT91S_PIO * pio, int mask, unsigned long val, int opcion)
23 {
24 if (opcion == 1)
25 pio->PIO_SODR = mask & val;
26 else
27 pio->PIO_CODR = mask & val;
28 }
29
30
31 int pio_in(AT91S_PIO * pio, int mask)
32 {
33 return (pio->PIO_PDSR & mask);
34 }
35
36
37 AT91S_PIO *pio_map(unsigned int piobase)
38 {
39 int fd;
40 void *base;
41
42 AT91S_PIO *pio;
43
44 off_t addr = piobase;
45
46 if ((fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1) {
47 fprintf(stderr, "Cannot open /dev/mem.\n");
48 exit(EXIT_FAILURE);
49 }
50
51 fprintf(stderr, "/dev/mem opened.\n");
52
53 base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, addr & ~MAP_MASK);
54
55 if (base == (void *) -1) {
56 fprintf(stderr, "Cannot open /dev/mem.\n");
57 exit(EXIT_FAILURE);
58 }
59
60 fprintf(stderr, "Memory mapped at address %p.\n", base);
61
62 pio = base + (addr & MAP_MASK);
63
64 return pio;
65 }
66
67
68 void pio_enable(AT91S_PIO * pio, int mask)
69 {
70 pio->PIO_PER = mask; /* Enable PIO */
71 }
72
73 void pio_output_enable(AT91S_PIO * pio, int mask)
74 {
75 pio->PIO_OER = mask; /* Set TDI, TMS and TCK as outputs */
76 }
77
78 void pio_input_enable(AT91S_PIO * pio, int mask)
79 {
80 pio->PIO_ODR = mask; /* Set TDO as input */
81 pio->PIO_IFER = mask; /* Enable Input Filter */
82 }
83
84 void pio_disable_irq(AT91S_PIO * pio, int mask)
85 {
86 pio->PIO_IDR = mask; /* Disable pin interrupts */
87 }
88
89 void pio_disable_multiple_driver(AT91S_PIO * pio, int mask)
90 {
91 pio->PIO_MDDR = mask; /* Disable Multiple Diver */
92 }
93
94 void pio_disable_pull_ups(AT91S_PIO * pio, int mask)
95 {
96 pio->PIO_PUDR = mask; /* Disable Pull-Ups */
97 }
98
99 void pio_synchronous_data_output(AT91S_PIO * pio, int mask)
100 {
101 pio->PIO_OWDR = mask; /* Synchronous Data Output Write in PIO_ */
102 }
103
104 //Nuevas funciones:
105 int ver_registro(AT91S_PIO * pio){
106 return (pio->PIO_PSR);
107 }
108 //Habilitar pines para usar con ADC
109 void pin_adc_enable(AT91S_PIO * pio, int mask){
110 pio->PIO_PDR = mask;
111 }
112 //selecciona para el periferico A
113 void periferico_a(AT91S_PIO * pio, int mask){
114 pio->PIO_ASR = mask;
115 }
116 //Retorna cero si esta en el perifierico A y 1 si est aen el periferico B
117 int ver_periferico(AT91S_PIO * pio){
118 return (pio->PIO_ABSR & 0x01);
119 }
Show file before | Show file after | Hide comments
@@ -0,0 +1,55
1 /*
2 * This programmer uses AT91' System clock
3 *
4 * 2010 by Ricardo V. Rojas Quispe
5 */
6
7 #include <stdint.h>
8 #include <stdlib.h>
9 #include <stdio.h>
10 #include <unistd.h>
11
12 #include <sys/types.h>
13 #include <sys/stat.h>
14 #include <sys/mman.h>
15 #include <fcntl.h>
16
17 #include "./Librerias/at91sysclock.h"
18
19 //Mapeando los registro en memoria:
20 AT91S_PMC *clock_map(unsigned int clockbase){
21 int fd;
22 void *base;
23
24 AT91S_PMC *clock;
25
26 off_t addr = clockbase;
27
28 if ((fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1) {
29 fprintf(stderr, "Cannot open /dev/mem.\n");
30 exit(EXIT_FAILURE);
31 }
32
33 //fprintf(stderr, "/dev/mem opened.\n");
34
35 base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, addr & ~MAP_MASK);
36
37 if (base == (void *) -1) {
38 fprintf(stderr, "Cannot open /dev/mem.\n");
39 exit(EXIT_FAILURE);
40 }
41
42 //fprintf(stderr, "Memory mapped at address %p.\n", base);
43
44 clock = base + (addr & MAP_MASK);
45
46 return clock;
47 }
48 //Habilitamos el clock de ADC
49 void enable_clock_adc(AT91S_PMC * clock){
50 clock->PMC_PCER=0x20;
51 }
52 //Leemos el registro de estado de clock para perifericos
53 unsigned int status_clock_adc(AT91S_PMC * clock){
54 return (clock->PMC_PCSR);
55 }
Show file before | Show file after | Hide comments
@@ -25,9 +25,14
25 25 #include <netinet/in.h>
26 26 #include <arpa/inet.h>
27 27 #include <netdb.h>
28
29 #include "./Librerias/AT91gpio_Funciones.h"
30 #include "./Librerias/Mensajes.h"
28 #include <time.h>
29 #include <math.h>
30
31 #include "./Librerias/at91gpio.h"
32 //#include "./Librerias/Mensajes.h"
33 #include "./Librerias/at91adc.h"
34 //clock
35 #include "./Librerias/at91sysclock.h"
31 36
32 37 #define PUERTO_SERVIDOR 5500
33 38 #define TAM_BUFFER 1024
@@ -45,6 +50,22
45 50
46 51 #define MyID 11
47 52 #define MAXPENDING 5 /* Maximum outstanding connection requests */
53
54 //parameters for the name of the output file
55 #define FPRE "AD" //prefix for the output file name
56 #define FEXT ".out" //file extension for the output file
57 #define FNAMELEN 40
58
59 //ADC parameters
60 #define REP 1 //defines how many times the data acquisation loop is repeated
61 #define NSAMPLES 100 //defines how many samples are taken in one data acqu-
62 // isation loop
63 #define CNVTIME 14.3 //defines how long it takes to get one sample. Value
64 // is only needed for the output file, doesn't change
65 // any ADC configurations
66 #define UREF 3.3 //Reference Voltage of ADC (max. ADC Voltage)
67 #define ADCRES 1023 //Resolution of ADC (10bit=1023)
68
48 69
49 70 char *buff_experimento= NULL;
50 71
@@ -86,6 +107,25
86 107 void SplitFrame(char *frame);
87 108 void intToStr( int number, char* str );
88 109
110 //ABS monitoring
111 int ABS_monitoreo(int sel_atenuador, int sel_calibracion, float umbral, int pulsewidth);
112
113 AT91S_ADC * configADC1(void);
114 AT91S_ADC * configADC2(void);
115
116 FILE * create_Output(char*, time_t);
117
118 void writeOutput(float resultado, FILE * output);
119
120 int checkTx(long int results1[],long int results2[], float umbral, int pulsewidth);
121
122 double mediana(long int *results, unsigned int cuenta);
123 float getPhase(long int results1[], long int results2[]);
124
125 int fExists(char *);
126 int configCLK();
127 //
128
89 129 /*
90 130 *
91 131 */
@@ -138,14 +178,16
138 178 /* Se establece el socket */
139 179 servSocket = socket(AF_INET,SOCK_STREAM, IPPROTO_TCP);
140 180 if (servSocket == -1){
141 ERROR_FATAL("No se establecio correctamente el socket: socket()\n");
181 printf("No se establecio correctamente el socket: socket()\n");
182 //ERROR_FATAL("No se establecio correctamente el socket: socket()\n");
142 183 exit(-1);
143 184 }
144 185
145 186 /* Se asocia el socket a un puerto y una IP */
146 187 resultado = bind(servSocket,(struct sockaddr *)&inf_servidor,sizeof(inf_servidor));
147 188 if (resultado== -1){
148 ERROR_FATAL("No se establecio correctamente el socket: bind()\n");
189 printf("No se establecio correctamente el socket: bind()\n");
190 //ERROR_FATAL("No se establecio correctamente el socket: bind()\n");
149 191 exit(-1);
150 192 }
151 193
@@ -287,7 +329,9
287 329 SplitFrame(rx_buffer);
288 330
289 331 if ((cmd == NULL) || (rx_data == NULL)){
290 ERROR("procesarPeticion: formato de mensaje incorrecto");
332 printf("procesarPeticion: formato de mensaje incorrecto");
333 //ERROR("procesarPeticion: formato de mensaje incorrecto");
334
291 335 }
292 336 else{
293 337 if(strcmp(cmd,"SNDF") == 0){
@@ -304,6 +348,7
304 348 }
305 349 else if(strcmp(cmd,"ANST") == 0){
306 350 tx_data = chequeo_sistema(filename2,rx_data);
351 ABS_monitoreo(1, 1, 50, 10);
307 352 printf("%s\n",tx_data);
308 353 }
309 354 else if(strcmp(cmd,"NTST") == 0){
@@ -314,7 +359,8
314 359 else{
315 360 tx_data = (char*)malloc(6);
316 361 tx_data = "Error";
317 ERROR("procesa_peticion: comando no reconocido");
362 printf("procesa_peticion: comando no reconocido");
363 //ERROR("procesa_peticion: comando no reconocido");
318 364 }
319 365
320 366 tx_len = malloc(7);
@@ -370,7 +416,8
370 416
371 417 Archivo_Fd = fopen(nombre_archivo,"r"); // Se procede a abrir el archivo, segun la ruta especificada
372 418 if(!Archivo_Fd){
373 ERROR("carga_archivo: No se pudo abrir el archivo!!! --> fopen()\n");
419 printf("carga_archivo: No se pudo abrir el archivo!!! --> fopen()\n");
420 //ERROR("carga_archivo: No se pudo abrir el archivo!!! --> fopen()\n");
374 421 return -1;
375 422 }else{
376 423
@@ -559,3 +606,418
559 606 str[(index-1)-position] = tmp;
560 607 }
561 608 }
609
610
611 //*****************************************************************
612 //ABS_monitoreo es la funci�n principal del proyecto ABS_Monitoreo.
613 //Esta funci�n es la que se debe agregar en otros c�digos.
614 //*****************************************************************
615 int ABS_monitoreo(int sel_atenuador, int sel_calibracion, float umbral, int pulsewidth){
616
617 //local variables
618 AT91S_PIO *pioc;
619 pioc = pio_map(PIOC_BASE);
620 unsigned int mask_sel_canal =PC4; //Aqu� se indican los pines que se desean usar como salidas. Las constantes PCx est�n defiidas en el header at91gpio.h
621 unsigned int mask_sel_atenuacion =PC5;
622 unsigned int mask_sel_calibracion =PC6;
623 AT91S_ADC *padc;
624 AT91S_ADC *padd;
625 FILE *fp;
626 long int results1[NSAMPLES], results2[NSAMPLES], results3[NSAMPLES], results4[NSAMPLES];
627 unsigned int i=0;
628 char fname[FNAMELEN];
629 int j=0;
630 time_t now;
631 FILE *archivo;
632 float phase1;
633 float phase2;
634 //system("./map_clock");
635
636 if (configCLK() == 1)
637 printf("clock ADC enable.\n");
638
639
640 //configurar tres pines como salida usando als m�scaras mask_sel_canal, mask_sel_atenuacion y mask_sel_calibracion. En este caso corresponden a los pines pc4, pc5 y pc6.
641 pio_enable(pioc, mask_sel_canal);
642 pio_enable(pioc, mask_sel_atenuacion);
643 pio_enable(pioc, mask_sel_calibracion);
644 pio_output_enable(pioc, mask_sel_canal); //configurar pc4 como salida
645 pio_output_enable(pioc, mask_sel_atenuacion); //configurar pc5 como salida
646 pio_output_enable(pioc, mask_sel_calibracion); //configurar pc6 como salida
647
648
649 //Se modifican las salidas correspondientes a la selecci�n del atenuador y calibraci�n, de acuerdo a los par�metros ingresados en la funci�n ABS_monitoreo.
650 pio_out(pioc, mask_sel_atenuacion, sel_atenuador,1);
651 pio_out(pioc, mask_sel_calibracion, sel_calibracion,1);
652
653
654 strcpy (fname, "/mnt/sd/archivos/absmonitoreo.txt"); //Direcci�n y nombre del archivo donde se desea guardar los datos.
655
656 if (fExists(fname)==0){ //si el archivo no existe, crea uno y le asigna el titulo
657 archivo = fopen(fname,"a+");
658 fprintf(archivo,"%s"," Registro de datos del ABS Control \n");
659 fprintf(archivo,"%s"," Fecha y hora Fase UP Fase DOWN\n");
660 fclose(archivo);
661 }
662
663
664 //configure ADC Settings
665 padc=configADC1();
666 padd=configADC2();
667
668 while (1){
669
670 ENABLE_CHANNEL(padc, ADC_CH0+ADC_CH1);
671 printf("\nAdquiriendo datos...\n"); //Indica en el terminal que se est�n adquiriendo datos (muestreando la se�al).
672
673
674 now = time(0); //Get current Time for File Name
675
676
677 //Se pone la salida de selecci�n de canal para seleccionar el canal 1 del detector de fase
678 pio_out(pioc, mask_sel_canal, 0,1);
679
680
681 //Se toman muestras para el canal 1 del detector de fase
682 while(1){
683 for(i=0; i < NSAMPLES; i++){
684
685 ADC_INIT(padc);
686 results1[i] = GET_ADC0(padc);
687 results2[i] = GET_ADC1(padd);
688 }
689
690
691 if (checkTx(results1, results2, umbral, pulsewidth)==1){ //Se verifica que las muestras tomadas del canal 1 del datector de fase //correspondan a un pulso.
692 break;
693 }
694 }
695
696
697 //Se pone la salida de selecci�n de canal para seleccionar el canal 2 del detector de fase
698 pio_out(pioc, mask_sel_canal, 1,1);
699
700
701
702 //Setoman muestras para el canal 2 del detector de fase
703 while(1){
704 for(i=0; i < NSAMPLES; i++){
705
706 ADC_INIT(padc);
707 results3[i] = GET_ADC0(padc);
708 results4[i] = GET_ADC1(padd);
709 }
710
711 if (checkTx(results3, results4, umbral, pulsewidth)==1){ //Se verifica que las muestras tomadas del canal 2 del detector de fase //correspondan a un pulso.
712 break;
713 }
714 }
715
716
717 //Una vez que se ha encontrado un pulso en cada canal, se calcula la fase de ambos.
718
719 phase1 = getPhase(results1, results2); //Calcular la fase del canal 1 del detector de fase.
720 phase2 = getPhase(results3, results4); //Calcular la fase del canal 2 del detector de fase.
721 //create Output File
722
723 strcpy (fname, "/mnt/sd/archivos/absmonitoreo.txt");
724 printf("\nTerminada la prueba # %d \n", j++);
725 fp=create_Output(fname, now); //Coloca la fecha y la hora en el archivo de texto
726 printf("mediana ch1 = %1.2f\n", phase1); //muestra resultado en terminal
727 printf("mediana ch2 = %1.2f\n", phase2); //muestra resultado en terminal
728 writeOutput(phase1, fp); //graba el resultado en el archivo de texto
729 writeOutput(phase2, fp); //graba el resultado en el archivo de texto
730 fprintf(fp, "\n"); //Pasa a la siguiente l�nea del archivo de texto
731 fclose(fp);
732 printf("Resultado guardado en %s \n", fname);
733
734 sleep(1);
735
736 }
737 return 0;
738 }
739 /*=============================================================================
740 Function definitions
741 =============================================================================*/
742
743 // Configures ADC registers in order to get a sample every 10us
744 AT91S_ADC * configADC1(void){
745 //Variables a usar:
746 unsigned int maskc_adc =PC0; //Usamos ADC0 y ADC1
747
748 //configuro pin:
749 AT91S_PIO *pioc;
750 pioc = pio_map(PIOC_BASE);
751 pin_adc_enable(pioc,maskc_adc); //Habilitamos PC0 para usar con ADC0 y 1
752 pio_disable_irq(pioc, maskc_adc);
753 pio_disable_multiple_driver(pioc, maskc_adc);
754 pio_disable_pull_ups(pioc, maskc_adc);
755 pio_input_enable(pioc, maskc_adc);
756
757
758 //Configuro el ADC:
759 AT91S_ADC *padc;
760
761 padc = adc_map1(ADC_BASE);
762
763 //clock ADC = 1MHz
764 //time startup = 8us
765 //time sample and hold = 2us
766 // hold
767 // ___________
768 // start ___________| |___________
769 //
770 // | --1.2us-- | --0.15us-- |
771 //ADC_RESET(padc);
772 CONFIG_ADC(padc,ADC_TRGEN_DIS | ADC_RES_10BIT | ADC_SLEEP_NORMAL_MODE | ADC_PRESCAL | ADC_STARTUP | ADC_SHTIM);
773 ENABLE_CHANNEL(padc,ADC_CH0); //habilito canal 0
774
775
776 return padc;
777 }
778
779 AT91S_ADC * configADC2(void){
780 //Variables a usar:
781 unsigned int maskc_adc =PC1; //Usamos ADC0 y ADC1
782
783 //configuro pin:
784 AT91S_PIO *piod;
785 piod = pio_map(PIOC_BASE);
786 pin_adc_enable(piod,maskc_adc); //Habilitamos PC0 para usar con ADC0 y 1
787 pio_disable_irq(piod, maskc_adc);
788 pio_disable_multiple_driver(piod, maskc_adc);
789 pio_disable_pull_ups(piod, maskc_adc);
790 pio_input_enable(piod, maskc_adc);
791
792 //Configuro el ADC:
793 AT91S_ADC *padd;
794
795 padd = adc_map1(ADC_BASE);
796
797 //clock ADC = 1MHz
798 //time startup = 8us
799 //time sample and hold = 2us
800 // hold
801 // ___________
802 // start ___________| |___________
803 //
804 // | --1.2us-- | --0.15us-- |
805 //ADC_RESET(padc);
806 CONFIG_ADC(padd,ADC_TRGEN_DIS | ADC_RES_10BIT | ADC_SLEEP_NORMAL_MODE | ADC_PRESCAL | ADC_STARTUP | ADC_SHTIM);
807 ENABLE_CHANNEL(padd,ADC_CH1); //habilito canal 1
808 return padd;
809 }
810
811
812 //++++++++++++++++++++
813
814 //creats the output file with a timestamp in the name
815 FILE * create_Output(char *fname, time_t rawtime){
816 FILE *file;
817 char timestamp[80];//, counter[5]="dcv";
818 //char str[4];
819 struct tm * timeinfo;
820
821 //format time
822 timeinfo = localtime ( &rawtime );
823 strftime (timestamp,sizeof(timestamp),"%a %y-%m-%d %H:%M:%S %Z",timeinfo);
824
825
826 //Creates the file name out of the #define parameters
827
828 strcpy (fname, "/mnt/sd/archivos/absmonitoreo.txt");
829 file = fopen(fname,"a+");
830 fprintf(file,"%s", timestamp);
831 //printf("\nTerminada la prueba # %d. Guardando resultado en %s\n",r, fname);
832 //printf("\nTerminada la prueba # %d/%d. Writing data to the file %s\n",r+1 , REP, fname);
833 //printf("\nAAAAAAAAAA %d...%s\n", counter[1], fname);
834 // return file pointer
835 return file;
836 }
837
838 //++++++++++++++++++++
839
840 //tests if a file already exists. returns 1 if it exists and 0 if it doesn't
841
842
843
844 //Funci�n checkTx verifica que la se�al muestreada corresponda a un pulso.
845 //results1 y results2 son los arreglos que contienen los datos muestreados por ambos canales del ADC del embebido.
846 //umbral indica qu� valor debe superar una muestra para considerarla un posible pulso o pico.
847 //pulsewidth indica cu�ntas muestras consecutivas deben superar el umbral para que se considere que se ha detectado un pulso.
848 int checkTx(long int results1[],long int results2[], float umbral, int pulsewidth){
849
850 int i, cont;
851 float z[NSAMPLES], sum, avg;
852 int isSignal, pulse;
853
854 for(i=0;i<NSAMPLES;i++){
855
856 z[i] =sqrt(1.0*results1[i]*results1[i]+1.0*results2[i]*results2[i]);
857 }
858
859 pulse = 0;
860 isSignal = 0;
861 cont =0;
862
863 sum = 0;
864 for(i=0;i<NSAMPLES;i++){
865
866 sum += z[i];
867 avg = sum/(i+1);
868 if ((z[i] - avg) > umbral){
869 if (isSignal == 1){
870 cont += 1;
871 }
872 if (cont == pulsewidth){
873 pulse = 1;
874 break;
875 }
876 isSignal = 1;
877 continue;
878 isSignal = 0;
879 cont = 0;
880 }
881 }
882
883 return pulse; //devuelve un entero: 1 si se ha detectado pulso, de lo contrario, 0.
884 }
885
886
887 int fExists(char * fname){
888 FILE * file;
889
890 file = fopen (fname, "r");
891 if (file == NULL)
892 {
893 return 0;
894 }
895 fclose(file);
896 return 1;
897 }
898
899
900 //Funci�n que calcula la mediana de un conjunto de muestras
901 double mediana(long int *results,unsigned int cuenta){
902 unsigned int i=0,j=0,aux=0;
903
904 double median=0;
905 /*Calculo mediana */
906
907 for(i=0;i<cuenta-1;i++){
908 for (j=i+1;j<cuenta;j++){
909 if(results[i]>results[j] ){
910
911 aux=results[i];
912 results[i]=results[j];
913 results[j]=aux;
914
915 }
916 }
917
918 }
919 median=results[cuenta/2];
920 return median;
921 }
922
923
924
925 //Funci�n que halla la fase de la se�al.
926 //Tiene como entradas las muestras correspondientes a la parte real e imaginaria de la se�al.
927 float getPhase(long int results1[],long int results2[]){
928
929 unsigned int count=0, i=0,umbral=1000;
930 //long int results1[];
931 //long int results2[];
932 long int power[NSAMPLES];
933 long int sumI=0,sumQ=0,I[NSAMPLES], Q[NSAMPLES],II[NSAMPLES], QQ[NSAMPLES];
934 double median1=0,median2=0;
935 long int promedioI=0,promedioQ=0;/*Calculo mediana 1*/
936 float resultado=0;
937
938 for(i=0;i<NSAMPLES;i++){
939
940 I[i] =results1[i];
941 Q[i] =results2[i];
942 }
943
944 /*Calculo mediana 1*/
945 median1=mediana(I,NSAMPLES);
946
947 /*Calculo mediana 2*/
948 median2=mediana(Q,NSAMPLES);
949
950
951
952
953
954
955 for(i=0;i<NSAMPLES;i++){
956
957 I[i] =results1[i];
958 Q[i] =results2[i];
959
960 }
961
962
963
964 for(i = 0; i < NSAMPLES ; i++){
965
966 I[i]=(I[i]-median1);
967 Q[i]=(Q[i]-median2);
968
969 }
970
971 for(i = 0; i < NSAMPLES ; i++){
972
973 power[i]=I[i]*I[i]+Q[i]*Q[i];
974
975 if(power[i] > umbral)
976 {
977
978 II[count]=I[i];
979 QQ[count]=Q[i];
980 count=count+1;
981
982 }
983
984 }
985
986 for(i = 0; i < count ; i++){
987
988 sumI=sumI+II[i];
989 sumQ=sumQ+QQ[i];
990
991 }
992
993 promedioI=sumI;
994 promedioQ=sumQ;
995
996 resultado = atan2(1.0*promedioI,1.0*promedioQ)*180/3.1416+62-44;
997
998
999 return resultado;
1000
1001 }
1002
1003
1004
1005 //Funci�n que muestra la fase detectada en el terminal y tambi�n la graba en el archivo de texto.
1006 void writeOutput(float resultado, FILE * output){
1007
1008
1009 //
1010
1011 fprintf(output," %1.2f ",resultado); //graba resultado en archivo .txt
1012 //
1013
1014 }
1015
1016 int configCLK(){
1017 //configuro pin:
1018 AT91S_PMC *sys_clock;
1019 sys_clock = clock_map(CLOCK_BASE);
1020 enable_clock_adc(sys_clock);
1021 //printf("clock ADC enable.\n");
1022 return 1;
1023 }
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