at91adc.h
124 lines
| 6.5 KiB
| text/x-c
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CLexer
| r116 | // ***************************************************************************** | |||
| // SOFTWARE API DEFINITION FOR Analog to Digital Convertor | ||||
| // ***************************************************************************** | ||||
| #ifndef ADC_AT91_H | ||||
| #define ADC_AT91_H | ||||
| #define MAP_SIZE 4096Ul | ||||
| #define MAP_MASK (MAP_SIZE - 1) | ||||
| #define ADC_BASE 0xFFFE0000 | ||||
| // -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- | ||||
| #define ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset | ||||
| #define ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion | ||||
| // -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- | ||||
| #define ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software | ||||
| #define ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. | ||||
| #define ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 | ||||
| #define ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 | ||||
| #define ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 | ||||
| #define ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 | ||||
| #define ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 | ||||
| #define ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 | ||||
| #define ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger | ||||
| #define ADC_RES_10BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution | ||||
| #define ADC_RES_8BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution | ||||
| #define ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode | ||||
| #define ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode | ||||
| #define ADC_PRESCAL ((unsigned int) 0x31 << 2) // (ADC) Prescaler rate selection | ||||
| #define ADC_STARTUP ((unsigned int) 0x00 << 2) // (ADC) Startup Time | ||||
| #define ADC_SHTIM ((unsigned int) 0x01 << 9) // (ADC) Sample & Hold Time | ||||
| // -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- | ||||
| #define ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 | ||||
| #define ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 | ||||
| #define ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 | ||||
| #define ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 | ||||
| /*Anadido por DCordova*/ | ||||
| // -------- ADC_CHSR : (ADC Offset: 0x10) ADC Channel Status Register -------- | ||||
| #define ADC_CHSR0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 | ||||
| #define ADC_CHSR1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 | ||||
| #define ADC_CHSR2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 | ||||
| #define ADC_CHSR3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 | ||||
| /*Anadido por DCordova*/ | ||||
| // -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- | ||||
| // -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- | ||||
| // -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- | ||||
| #define MASK_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion | ||||
| #define MASK_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion | ||||
| #define MASK_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion | ||||
| #define MASK_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion | ||||
| #define MASK_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error | ||||
| #define MASK_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error | ||||
| #define MASK_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error | ||||
| #define MASK_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error | ||||
| #define MASK_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready | ||||
| #define MASK_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun | ||||
| // -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- | ||||
| #define ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted | ||||
| #define ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data | ||||
| #define ADC_DISABLE_INTERRUP ((unsigned int) 0x0F0F0F << 0) //(ADC) Disable all interrup | ||||
| typedef volatile unsigned int AT91_REG2;// Hardware register definition | ||||
| typedef struct _AT91S_ADC { | ||||
| AT91_REG2 ADC_CR; // ADC Control Register | ||||
| AT91_REG2 ADC_MR; // ADC Mode Register | ||||
| AT91_REG2 Reserved0[2]; // | ||||
| AT91_REG2 ADC_CHER; // ADC Channel Enable Register | ||||
| AT91_REG2 ADC_CHDR; // ADC Channel Disable Register | ||||
| AT91_REG2 ADC_CHSR; // ADC Channel Status Register | ||||
| AT91_REG2 ADC_SR; // ADC Status Register | ||||
| AT91_REG2 ADC_LCDR; // ADC Last Converted Data Register | ||||
| AT91_REG2 ADC_IER; // ADC Interrupt Enable Register | ||||
| AT91_REG2 ADC_IDR; // ADC Interrupt Disable Register | ||||
| AT91_REG2 ADC_IMR; // ADC Interrupt Mask Register | ||||
| AT91_REG2 ADC_CDR0; // ADC Channel Data Register 0 | ||||
| AT91_REG2 ADC_CDR1; // ADC Channel Data Register 1 | ||||
| AT91_REG2 ADC_CDR2; // ADC Channel Data Register 2 | ||||
| AT91_REG2 ADC_CDR3; // ADC Channel Data Register 3 | ||||
| AT91_REG2 ADC_CDR4; // ADC Channel Data Register 4 | ||||
| AT91_REG2 ADC_CDR5; // ADC Channel Data Register 5 | ||||
| AT91_REG2 ADC_CDR6; // ADC Channel Data Register 6 | ||||
| AT91_REG2 ADC_CDR7; // ADC Channel Data Register 7 | ||||
| AT91_REG2 Reserved1[44]; // | ||||
| AT91_REG2 ADC_RPR; // Receive Pointer Register | ||||
| AT91_REG2 ADC_RCR; // Receive Counter Register | ||||
| AT91_REG2 ADC_TPR; // Transmit Pointer Register | ||||
| AT91_REG2 ADC_TCR; // Transmit Counter Register | ||||
| AT91_REG2 ADC_RNPR; // Receive Next Pointer Register | ||||
| AT91_REG2 ADC_RNCR; // Receive Next Counter Register | ||||
| AT91_REG2 ADC_TNPR; // Transmit Next Pointer Register | ||||
| AT91_REG2 ADC_TNCR; // Transmit Next Counter Register | ||||
| AT91_REG2 ADC_PTCR; // PDC Transfer Control Register | ||||
| AT91_REG2 ADC_PTSR; // PDC Transfer Status Register | ||||
| } AT91S_ADC, *AT91PS_ADC; | ||||
| AT91S_ADC *adc_map(unsigned int adcbase); | ||||
| /**********************Aniadido por DCV*********/ | ||||
| AT91S_ADC *adc_map1(unsigned int adcbase); | ||||
| /**********************Aniadido por DCV*********/ | ||||
| void ADC_INIT(AT91S_ADC * adc); | ||||
| void ADC_RESET(AT91S_ADC * adc); | ||||
| void CONFIG_ADC(AT91S_ADC * adc,unsigned int REG_CONFIG); | ||||
| void ENABLE_CHANNEL(AT91S_ADC * adc,unsigned int CHANNEL); | ||||
| unsigned int STATUS_CHANNEL(AT91S_ADC * adc); | ||||
| unsigned int GET_ADC(AT91S_ADC * adc); | ||||
| unsigned int GET_ADC0(AT91S_ADC * adc); | ||||
| unsigned int GET_ADC1(AT91S_ADC * adc); | ||||
| unsigned int GET_ADC3(AT91S_ADC * adc); | ||||
| unsigned int ver_reg_mode(AT91S_ADC * adc); | ||||
| unsigned int GET_STATUS(AT91S_ADC * adc); | ||||
| #endif | ||||
