at91sysclock.h
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| 5.3 KiB
| text/x-c
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| r116 | // ***************************************************************************** | |||
| // SOFTWARE API DEFINITION FOR Power Management Controler | ||||
| // ***************************************************************************** | ||||
| #ifndef SYSCLOCK_AT91_H | ||||
| #define SYSCLOCK_AT91_H | ||||
| #define MAP_SIZE 4096Ul | ||||
| #define MAP_MASK (MAP_SIZE - 1) | ||||
| #define CLOCK_BASE 0xFFFFFC00 | ||||
| // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- | ||||
| #define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock | ||||
| #define AT91C_PMC_UHP ((unsigned int) 0x1 << 6) // (PMC) USB Host Port Clock | ||||
| #define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock | ||||
| #define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output | ||||
| #define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output | ||||
| #define AT91C_PMC_HCK0 ((unsigned int) 0x1 << 16) // (PMC) AHB UHP Clock Output | ||||
| #define AT91C_PMC_HCK1 ((unsigned int) 0x1 << 17) // (PMC) AHB LCDC Clock Output | ||||
| // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- | ||||
| // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- | ||||
| // -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- | ||||
| // -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- | ||||
| // -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- | ||||
| // -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register -------- | ||||
| // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- | ||||
| #define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection | ||||
| #define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected | ||||
| #define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected | ||||
| #define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) // (PMC) Clock from PLL A is selected | ||||
| #define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL B is selected | ||||
| #define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler | ||||
| #define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock | ||||
| #define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 | ||||
| #define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 | ||||
| #define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 | ||||
| #define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 | ||||
| #define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 | ||||
| #define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 | ||||
| #define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) // (PMC) Master Clock Division | ||||
| #define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) // (PMC) The master clock and the processor clock are the same | ||||
| #define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock | ||||
| #define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) // (PMC) The processor clock is four times faster than the master clock | ||||
| // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- | ||||
| // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- | ||||
| #define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask | ||||
| #define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask | ||||
| #define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask | ||||
| #define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask | ||||
| #define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask | ||||
| #define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask | ||||
| // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- | ||||
| // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- | ||||
| // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- | ||||
| typedef volatile unsigned int AT91_REG3;// Hardware register definition | ||||
| typedef struct _AT91S_PMC { | ||||
| AT91_REG3 PMC_SCER; // System Clock Enable Register | ||||
| AT91_REG3 PMC_SCDR; // System Clock Disable Register | ||||
| AT91_REG3 PMC_SCSR; // System Clock Status Register | ||||
| AT91_REG3 Reserved0[1]; // | ||||
| AT91_REG3 PMC_PCER; // Peripheral Clock Enable Register | ||||
| AT91_REG3 PMC_PCDR; // Peripheral Clock Disable Register | ||||
| AT91_REG3 PMC_PCSR; // Peripheral Clock Status Register | ||||
| AT91_REG3 Reserved1[1]; // | ||||
| AT91_REG3 PMC_MOR; // Main Oscillator Register | ||||
| AT91_REG3 PMC_MCFR; // Main Clock Frequency Register | ||||
| AT91_REG3 PMC_PLLAR; // PLL A Register | ||||
| AT91_REG3 PMC_PLLBR; // PLL B Register | ||||
| AT91_REG3 PMC_MCKR; // Master Clock Register | ||||
| AT91_REG3 Reserved2[3]; // | ||||
| AT91_REG3 PMC_PCKR[8]; // Programmable Clock Register | ||||
| AT91_REG3 PMC_IER; // Interrupt Enable Register | ||||
| AT91_REG3 PMC_IDR; // Interrupt Disable Register | ||||
| AT91_REG3 PMC_SR; // Status Register | ||||
| AT91_REG3 PMC_IMR; // Interrupt Mask Register | ||||
| } AT91S_PMC, *AT91PS_PMC; | ||||
| //Funciones: | ||||
| AT91S_PMC *clock_map(unsigned int clockbase); | ||||
| void enable_clock_adc(AT91S_PMC * clock); | ||||
| unsigned int status_clock_adc(AT91S_PMC * clock); | ||||
| #endif | ||||
